1. Technical Field
The present invention relates to an improved data processing system and in particular to a method and apparatus for transferring data within a data processing system. Still more particularly, the present invention relates to a method and apparatus for synchronizing data transfer between components operating at different speeds within a data processing system.
2. Description of the Related Art
The designs of digital computers and work stations continue to evolve at a rapid pace as new processors (microprocessors/CPUs) become available and are integrated with input/output (I/O) resources into advanced versions of such systems. Though the widths of the multiple buses commonly present in such systems often vary from model to model, the prevailing and evolutionary changes between models tend to be associated with the clock rates of the processors. Namely, it is very common for a fundamental system design to be upgraded with faster processors in half a year or less increments of a model's life cycle. The problem is that the system boards are designed with buses and associated hardware which operate over a first relative frequency range while the processor clock frequencies vary over a second range of fundamentally higher frequencies.
A typical computer system is commonly comprised of a central processing unit (CPU), memory, and various buses which provide connection to peripherals. A commonly used bus is Peripheral Component Interconnect (PCI) which has become an industry standard. The PCI bus operates at a frequency of 33 MHz (or 66 MHz for limited high speed applications). The CPU may operate at a range of speeds, especially in embedded applications.
Peripherals such as network or storage interface controllers commonly have both clock rates and data transfer rates from the network or storage elements which are different than that supported by a 33 MHz PCI bus. In order to accommodate data transfers between the two different clock domains, an intermediate buffer stores data at one rate and reads out at another rate.
If low latency is desired between the arrival of data from one entity in a first clock domain, and its transfer to a second entity in a second clock domain, the designer is faced with the challenge of determining when data from the other clock domain has been written and is stable. For example, if data is transferred from a 40 MHz entity to a 33 MHz entity, the 40 MHz entity writes data to a register which results in a flag being set to indicate that data is available. The challenge is how to have a system in a second clock domain read the flag signal as soon as possible after data is written by the first clock domain, but to prevent the flag signal from being read while it is in transition which might result in indeterminate levels (metastability) or possibly erroneous values. First in, first out (FIFO) memories have been used to provide the speed matching capabilities between two clock domains. Fall through FIFO memories can accomplish this function, but at increased logic complexity and associated limits in speed of operation. Register based FIFO memories have been used for speed matching but typically incur a delay of one or two clocks to synchronize between the two clock domains.
Therefore, it would be advantageous to have an improved method and apparatus to allow register based FIFO memories to operate without incurring clock delays associated with presently available systems.